When a processor is adopted to process a specific task, it is necessary to abstract the task into a proper data structure, the basic type of which includes a set, a linear structure, a tree structure, a graphic structure and the like. Most of these structures are implemented by software, which is low in efficiency, complex to implement and relatively large in energy consumption. A stack is taken as an example below to show how the software implements a specific data structure.
The stack is a linear table in which insertion or deletion is performed only at the top and base of the stack. A process of implementing the stack by software includes: firstly, applying for storage space according to maximum usage amount of the stack, and setting a top pointer and a base pointer for the stack, during initialization, the stack is null and the top pointer points to the base, namely, the top is equal to the base; secondly, pushing data into the stack through a push instruction and adding 1 to the top for each push operation; and finally, popping the data stored in the stack through a pop instruction and subtracting 1 from the top for each pop operation. Here, the top and base pointers are stored in a register or a memory, and the operation of adding or subtracting 1 also needs to be completed through an instruction. A principle of implementing the stack by software is as shown in FIG. 1. It can be seen that at least two instructions are required for each operation of the stack and more instructions are required if it is necessary to implement an anti-coverage function or other functions of the stack, so that the processing efficiency of the stack is relatively low.
At present, hardware may be adopted to implement data structures, but only some data structures can be implemented, such as a First In First Out queue (FIFO), a stack, a heap, a queue, and other sets or linear structures. Since data structures implemented by the hardware are generally implemented by firmware, the data structures are poor in configurability and flexibility and waste system resources. An FIFO structure implemented by hardware is as shown in FIG. 2. It can be seen that the hardware FIFO includes read address generate, write address generate, a double-port RAM, and a full and empty flag of the FIFO. Moreover, the compatibility of input and output interfaces needs to be considered. The FIFO implemented by hardware is relatively high in efficiency and can be directly utilized without configuration, but the size, interface and the like of the FIFO are fixed. In addition, when a processor needs not to use the FIFO, the FIFO will be wasted since the FIFO cannot be used as a heap or other structures. Moreover, a tree structure cannot be reused and is relatively complex in design if implemented by hardware.